Current Sensing Topology Comparison: Shunt, Hall Effect, and Current Transformer at 20 A

Current sensing topology choice is not "which chip is cheapest" — it's which error mechanism you can tolerate at your frequency, isolation requirement, and acceptable power loss. I bench-compared shunt + INA240, Allegro ACS770 Hall sensor, and a PE-67100 current transformer at 20 A steady-state and 50 A 10 kHz pulses on a motor drive test fixture.

Test fixture

• Supply: Rigol DP832A + 24 V bus, low-inductance return
• Load: Electronic load (BK Precision 8601) + parallel MOSFET pulse generator for fast edges
• Ground truth: Yokogawa WT310E on same bus bar (0.1% claimed accuracy)
• DUT placements: Kelvin shunt layout, Hall sensor on same conductor, CT on feed-through

All signals captured on Siglent SDS1104X-E (100 MHz, 1 GSa/s), diff probe on shunt, single-ended on Hall/CT with attention to common-mode.

Topology 1: Shunt + INA240A2 (gain 50)

Parts: 500 µΩ shunt (Isabellenhütte BVR), TI INA240A2, 3.3 V ADC (STM32G474 12-bit).

Sweet spot

• DC to ~100 kHz bandwidth (layout dependent)
• Best absolute accuracy in our test: ±0.4% at 20 A after two-point cal
• Lowest parts cost (~$4 shunt + $2 amp)

Tradeoffs measured

• Power loss: I²R = 20² × 500 µΩ = 200 mW at 20 A — fine. At 50 A pulse: 1.25 W — shunt heated, drift +0.3% until thermal equilibrium
• Common-mode: INA240 rated 80 V CM; fine on low-side shunt. High-side at 400 V bus needs different amp (INA240 not enough)
• Layout sensitivity: 2 mm trace mismatch between Kelvin sense pairs added 8 mA offset at zero — layout is part of spec

When I'd pick it

Motor control below 100 A, low-side sensing, cost-sensitive, MCU ADC available. Default choice.

Topology 2: Hall effect (Allegro ACS770LCB-100B-PFF-T)

Sweet spot

• Galvanic isolation without opto isolation amplifier
• Moderate bandwidth: datasheet 120 kHz, measured -3 dB ~85 kHz on our bar
• No insertion loss (conductor through package)

Tradeoffs measured

• Offset drift: ±20 mA zero offset at 25°C → ±0.1% at 20 A if lucky, ±0.5% after 40°C board warm-up without temp comp
• Nonlinearity: ±0.8% full scale per datasheet; observed ±0.6% 5–50 A
• Response to pulse: 50 A step, rise time ~6 µs vs <1 µs shunt path — fine for thermal management, marginal for fast OCP

When I'd pick it

High-side sensing, isolation required, moderate accuracy OK (thermal management, energy metering B-tier). Not for precision servo current loops.

Topology 3: Current transformer (PE-67100, 100 A rated)

With burden resistor 10 Ω → 50 mV/A secondary (turns ratio 1:1000).

Sweet spot

• High current AC or pulsed AC component
• Excellent isolation
• Negligible DC path loss

Tradeoffs measured

• No DC response — by design. 20 A DC + 2 A ripple: measures ripple only; DC invisible
• Phase shift: 5° at 10 kHz on pulse fundamental — matters for power factor correction control loops
• Burden resistor sizing: 10 Ω gave 2:1 SNR vs 5 Ω but saturation risk on 50 A peak — had to verify core doesn't saturate

When I'd pick it

AC load monitoring, ground fault detection, retrofits where insertion loss unacceptable. Pair with shunt if DC component needed — we didn't on this bench.

Comparison table (20 A steady, 25°C)

Topology	Accuracy	Bandwidth	Isolation	Loss @ 20A	DC capable
Shunt + INA240	±0.4%	~100 kHz	None (low-side)	200 mW	Yes
Hall ACS770	±0.6%	~85 kHz	Yes	~0	Yes
CT + burden	N/A at DC	~300 kHz AC	Yes	~0	No

50 A pulse findings

• Shunt: fastest response, thermal drift during repeated pulses — needed copper area on shunt pads
• Hall: acceptable OCP detection latency (~8 µs to threshold compare)
• CT: excellent AC component of pulse; useless for DC bus holdup monitoring

ADC and front-end notes

STM32G474 12-bit, 3.3 V ref, 50 mV full-scale on shunt path → ~16 mA LSB. Oversampling to 14-bit effective got ~4 mA resolution — enough for thermal management, not for mA standby detection.

For standby, separate ACS712 low-range or dedicated coulomb counting — different problem.

See bench PSU notes part 3 for how current limit loops closed in my home lab supply — shunt topology again, different scale.

Power sequencing matters when sensor rail comes up after power stage — INA240 outputs undefined until 3.3 V stable; blind spot during startup.

Layout checklist for shunt accuracy

Kelvin sense trace rules we enforce in review:

1. Sense traces leave shunt pads on inner layer away from switch-node copper pour
2. No vias between shunt and INA240 inputs — single-layer pair preferred
3. Filter cap at INA240 supply pin, not at shunt
4. Keep Hall sensor ≥5 mm from switch-node inductor — magnetic crosstalk added 15 mA offset in one layout spin

Temperature drift during soak

Hall sensor offset drift after 30 min at 20 A: +8 mA without compensation, +2 mA with one-point cal at 40°C soak start. Shunt drift dominated thermal EMF at +3 mA unless copper area generous — Isabellenhütte shunt outperformed cheap metal strip.

What I'd do next

1. Test AMC1302 isolated delta-sigma for high-side 400 V bus — Hall alternative
2. Characterize ** Rogowski coil** for wide dynamic range AC
3. Build cal fixture with 0.05% reference shunt — trust but verify annually

Pick topology from frequency, isolation, and loss constraints — not from which eval board was in the drawer.