Oscilloscope Trigger Cheat Sheet for Embedded Work

Edge, pulse-width, serial decode, runt — a practical reference for the triggers I actually use when debugging firmware on real hardware. Not a scope manual; the subset that paid for itself on a Rigol DS1054Z and a borrowed Keysight DSOX3024T.

Why trigger choice matters

Wrong trigger → waveform rolls → you conclude "random noise." Right trigger → stable capture of the 3 µs glitch that happens once per second. Most of my wasted bench hours were trigger configuration, not probe technique.

Triggers I use weekly

Edge (default, but configure deliberately)

• Rising on CS — bracket SPI/I2C transactions. Set holdoff ~1 ms when multiple slaves share a bus.
• Falling on DRDY — delta-sigma ADC bring-up; pair with single-shot to catch first conversion after reset.
• Either edge on NRST — brown-out and reset sequencing debug.

Tip: 10% pre-trigger capture when you care what happened before the event (power rail sag before reset).

Pulse width

The workhorse for embedded:

Use case	Setting
Short glitch on enable line	< 500 ns
Missing clock stretch	SCL low > 5 µs
Watchdog bite window	RESET pulse width 100 µs – 10 ms
PWM duty sanity	high time within band

On the Rigol, pulse triggers are coarse below ~100 ns — fine for reset glitches, not for sub-100 ns SI work.

Pair with I2C glitch taxonomy when decode fails but pulse trigger on SCL low time finds stretching.

Runt

Catches pulses that cross threshold but don't reach valid high/low — classic symptom of:

• Undershoot on long wires
• Termination wrong on clock lines
• 1.8 V slave on 3.3 V pull-ups without proper Vih

Set runt threshold between 30% and 70% of expected swing. Saved us on a LIS3DH interrupt line with 22 kΩ pull-up on a noisy flex.

Timeout / gap

Trigger when signal stays above/below threshold longer than T — useful for:

• UART break detection
• I2C bus idle lock (SDA high, SCL high gap before unexpected START)
• SPI CS stuck active

Serial (SPI/I2C/UART decode triggers)

Keysight's hardware decode trigger ("trigger on I2C address 0x48 write") is worth the rental day rate for one nasty bug. Rigol's decode is usable at ≤1 MHz I2C for bring-up.

Workflow:

1. Enable decode, confirm address seen.
2. Trigger on specific data byte (e.g., WHO_AM_I read).
3. Single-shot reset sequence capture.

Cross-reference SPI CPOL/CPHA debugging when decode shows frames but data wrong — trigger is fine, mode is wrong.

Logic / pattern (when available)

Multi-channel pattern match on 4-bit parallel bus state — FPGA config pins, strap reads. Overkill for GPIO bit-bang; essential when boot mode straps are sampled once at POR.

Trigger modes

• Auto: never "lose" display — good for power rails, bad for rare events (scope retriggers on noise).
• Normal: waits for event — use for one-shot bugs.
• Single: arm once after reset button — standard for "capture first fault after power-up."

For EMI bench work, Normal + long persistence overlay shows jitter distribution on clock harmonics — not a trigger type, but display mode matters alongside edge trigger on sync clock.

Probe + trigger interaction

10× probe adds capacitance — narrow pulses disappear. When runt trigger never fires but eyes see glitches, switch to 1× carefully (bandwidth limit ON) or active probe if someone else's budget allows it.

Ground spring vs. six-inch ground lead can shift pulse width measurements by 2×. Fix mechanical before chasing firmware.

My bench presets (saved on USB)

1. SPI-CS-Rise-10ms-holdoff
2. I2C-START-then-ACK-fail (serial trigger NACK)
3. 3V3-rail-dip-below-3.0V (edge + width)
4. RESET-runt-1us-100us

Copy these names into your scope's save menu — naming discipline beats re-deriving from memory at 2 AM.

What I don't use often

• Window trigger — useful for DDR/ high-speed; rare on 10 MHz SPI.
• Setup/hold violation — FPGA teams live here; MCU shops seldom.
• RF envelope — spectrum analyzer domain.

What I'd do next

Document trigger preset per board in the hardware wiki — link from schematic net names to scope save file. Onboarding drops from "learn the bug" to "load preset 3."

If buying scope for embedded only: prioritize decode trigger + deep memory over bandwidth above 100 MHz unless you're doing USB HS eye diagrams.

Holdoff and glitch immunity

When CS toggles fast on shared SPI, re-triggering on every edge rolls the display. Set holdoff to slightly less than minimum inter-frame gap — for our 10 MHz SPI with 32-byte frames, ~30 µs holdoff stabilized capture.

Rigol: Trigger → Holdoff → Time. Keysight: Trigger → Holdoff.

Memory depth vs sample rate

Deep memory at moderate rate beats max rate with shallow memory for "find the one bad frame after reset." We capture at 2.5 MS/s on rails for 50 ms — enough pre/post trigger — then zoom digitally.

Bench power trigger trick

Bench supply current limit trip — edge trigger on current probe when rail collapses. Correlates software reset with brownout faster than guessing. Pair with power sequencing notes.

What I'd do next